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| Patent # | Description |
|---|---|
| US-8,082,529 |
Method and system for mapping a boolean logic network to a limited set of
application-domain specific logic cells A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are... |
| US-8,037,379 |
Prediction of impact on post-repair yield resulting from manufacturing
process modification A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data... |
| US-8,004,315 |
Process for making and designing an IC with pattern controlled layout
regions The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates... |
| US-7,969,199 |
Pattern controlled IC layout The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates... |
| US-7,935,965 |
Test structures and methods for electrical characterization of alignment
of line patterns defined with double... A test vehicle and method for electrical characterization of misalignment, for example resulting from double patterning processes, that enables characterization... |
| US-7,932,105 |
Systems and methods for detecting and monitoring nickel-silicide process
and induced failures Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a... |
| US-7,906,254 |
Method and process for design of integrated circuits using regular
geometry patterns to obtain geometrically... The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure... |
| US-7,902,852 |
High density test structure array to support addressable high accuracy
4-terminal measurements Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a... |
| US-7,894,926 |
Global predictive monitoring system for a manufacturing facility A global predictive monitoring system for a manufacturing facility. The system may be employed in an integrated circuit (IC) device fabrication facility to... |
| US-7,888,961 |
Apparatus and method for electrical detection and localization of shorts
in metal interconnect lines A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a... |
| US-7,827,516 |
Method and system for grouping logic in an integrated circuit design to
minimize number of transistors and... A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions... |
| US-7,807,480 |
Test cells for semiconductor yield improvement A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third... |
| US-7,784,013 |
Method for the definition of a library of application-domain-specific
logic cells The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the... |
| US-7,757,187 |
Method for mapping a Boolean logic network to a limited set of
application-domain specific logic cells A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are... |
| US-7,739,065 |
Inspection plan optimization based on layout attributes and process
variance Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from... |
| US-7,673,262 |
System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature... |
| US-7,644,388 |
Method for reducing layout printability effects on semiconductor device
performance A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or... |
| US-7,638,247 |
Method for electron beam proximity effect correction Optimized dose assignments are determined for each portion of a layout by utilizing an improved proximity function and additional dose correction functions in... |
| US-7,592,827 |
Apparatus and method for electrical detection and localization of shorts
in metal interconnect lines A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a... |
| US-7,568,180 |
Generalization of the photo process window and its application to OPC test
pattern design A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining... |
| US-7,529,642 |
Method for evaluating the quality of data collection in a manufacturing
environment A method for evaluating the quality of data collection in a manufacturing environment is provided. Said data are intended to be analyzed by a process control... |
| US-7,527,987 |
Fast localization of electrical failures on an integrated circuit system
and method Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures... |
| US-7,508,071 |
Adjusting die placement on a semiconductor wafer to increase yield A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or... |
| US-7,494,893 |
Identifying yield-relevant process parameters in integrated circuit device
fabrication processes In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process... |
| US-7,489,151 |
Layout for DUT arrays used in semiconductor wafer testing A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed... |
| US-7,487,474 |
Designing an integrated circuit to improve yield using a variant design
element An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in... |
| US-7,440,869 |
Mapping yield information of semiconductor dice In one exemplary embodiment, yield information of semiconductor dice is mapped by obtaining yield information of a first die that was formed on a first location... |
| US-7,434,197 |
Method for improving mask layout and fabrication A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries... |
| US-7,415,386 |
Method and system for failure signal detection analysis A method for analyzing a sample of wafers includes identifying F failure metrics applicable to at least one pattern on each wafer within the sample. Z spatial... |
| US-7,395,518 |
Back end of line clone test vehicle A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the... |
| US-7,373,625 |
System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature... |
| US-7,356,800 |
System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature... |
| US-7,348,594 |
Test structures and models for estimating the yield impact of dishing
and/or voids A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second... |
| US-7,334,205 |
Optimization of die placement on wafers A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing... |
| US-7,305,638 |
Method and system for ROM coding to improve yield A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a... |
| US-7,278,118 |
Method and process for design of integrated circuits using regular
geometry patterns to obtain geometrically... The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure... |
| US-7,220,605 |
Selecting dice to test using a yield map Dice on a wafer are selected to be tested using a yield map. The yield map incorporates yield information of different products produced by the same fabrication... |
| US-7,197,726 |
Test structures for estimating dishing and erosion effects in copper
damascene technology A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first... |
| US-7,190,183 |
Selecting die placement on a semiconductor wafer to reduce test time A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to... |
| US-7,174,521 |
System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature... |
| US-7,169,638 |
Adjusting die placement on a semiconductor wafer to increase yield A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or... |
| US-7,154,115 |
Zoom in pin nest structure, test vehicle having the structure, and method
of fabricating the structure A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the... |
| US-7,087,507 |
Implantation of deuterium in MOS and DRAM devices A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by... |
| US-7,047,505 |
Method for optimizing the characteristics of integrated circuits
components from circuit specifications A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation... |
| US-7,039,543 |
Transforming yield information of a semiconductor fabrication process Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each... |
| US-7,024,642 |
Extraction method of defect density and size distributions A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a... |
| US-7,003,742 |
Methodology for the optimization of testing and diagnosis of analog and
mixed signal ICs and embedded cores A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet... |
| US-6,978,229 |
Efficient method for modeling and simulation of the impact of local and
global variation on integrated circuits A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated... |
| US-6,901,564 |
System and method for product yield prediction A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit.... |
| US-6,892,367 |
Vertex based layout pattern (VEP): a method and apparatus for describing
repetitive patterns in IC mask layout A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained... |
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